1. Technical Field
The present invention relates to a bidirectional shift register which is used for, for example, a data line driving circuit or a scanning line driving circuit of liquid crystal, to an electro-optical device using such a driving circuit, and to an electronic apparatus.
2. Related Art
In the related art, as electro-optical devices in which an image is displayed in an image display region, liquid crystal display devices have been known. The liquid crystal display device has a data line driving circuit or a scanning line driving circuit, which supplies data line signals or scanning line signals to data lines or scanning lines wired in the image display region with a predetermined timing, for example. Such a data line driving circuit or a scanning line driving circuit has a bidirectional shift register that output sampling signals, such that image signals are written into respective pixels based on the sampling signals.
1: Configuration of Bidirectional Shift Register according to the Related Art
FIG. 14 is a circuit diagram of a part of a bidirectional shift register 100 constituted in a positive logic according to the related art.
The bidirectional shift register 100 includes n shift register unit circuits A1, A2, . . . , An, each having a plurality of thin film transistors, n−1 logical arithmetic unit circuits B1, B2, . . . , B(n−1). Here, n is a natural number of two or more.
Hereinafter, the shift register unit circuits A1 to A4 and the logical arithmetic unit circuits B1 to B3 will be described in detail. Of course, other shift register unit circuits A5 to An or logical arithmetic unit circuits B4 to B(n−1) have the same configuration as those of the shift register unit circuits A1 to A4 or those of the logical arithmetic unit circuits B1 to B3.
To each of the shift register unit circuits A1 to A4, a first clock signal CK1, a first inverted clock signal CK1B, a second clock signal CK2, and a second inverted clock signal CK2B are supplied. The shift register unit circuits A1 to A4 transmit a transmission start pulse ST in synchronization with the clock signals CK1, CK1B, CK2, and CK2B and outputs output signals P1 to P4, respectively. Here, to each of the shift register unit circuits A1 to A4, a transmission direction control signal DIR and an inverted transmission direction control signal DIRB are supplied, such that the transmission direction is controlled.
The logical arithmetic unit circuits B1 to B3 generate sampling signals Sm1 to Sm3 on the basis of the output signals P1 to P4 of the shift register unit circuits A1 to A4, respectively.
Specifically, the logical arithmetic unit circuit B is an AND circuit that calculates a positive logical product corresponding to two-stages of the shift register unit circuits A. That is, to the logical arithmetic unit circuit Bm (where m is a natural number of n−1 or less), the output signal Pm from the shift register unit circuit Am and the output signal P(m+1) from the shift register unit circuit Am+1 are input. The logical arithmetic unit circuit Bm calculates the logical product of the output signal Pm and the output signal P(m+1) and outputs the logical product as the sampling signal 5 mm.
Moreover, when the bidirectional shift register is constituted in a negative logic, the logical arithmetic unit circuit B is a NOR circuit that calculates a negative logical product corresponding to the shift register unit circuits A.
Each of the shift register unit circuits A1 to A4 has first and second clocked inverters 101 and 102, an inverter 103, and first and second transfer gates 104 and 105, for example. Output terminals of the first and second clocked inverters 101 and 102 are connected to an input terminal of the inverter 103, and an output terminal of the inverter 103 is connected to input terminals of the first and second clocked inverters 101 and 102 through the first and second transfer gates 104 and 105 (see JP-A-11-176186).
The first clock signal CK1 and the first inverted clock signal CK1B or the second clock signal CK2 and the second inverted clock signal CK2B are supplied to a control terminal of the first clocked inverter 101, and the others are supplied to a control terminal of the second clocked inverter 102.
The transmission direction control signal DIR is supplied to a control terminal of the first transfer gate 104, and the inverted transmission direction control signal DIRB is supplied to a control terminal of the second transfer gate 105. Accordingly, only one of the first and second transfer gates 104 and 105 is turned on, and then the transmission direction of the transmission start pulse ST is determined. Here, it is assumed that the logical level of the inverted transmission direction control signal DIRB is in the H level (high level). That is, all the first transfer gates 104 are in a high impedance state, and all the second transfer gates are in an ON state, such that the transmission start pulse ST is transmitted from the left side of FIG. 14 to the right side.
Next, the operations of the shift register unit circuits A1 to A4 will be described.
It is assumed that the transmission start pulse ST, which is in an active state at the time of the H level, is input, the first clock signal CK1 is in the H level, and the second clock signal CK2 is in the L level.
In this state, in the shift register unit circuit A1, the first clocked inverter 101 operates as an inverter having the input of the H level and the output of the L level (low level), and the output of the output signal P1 is in the H level.
On the other hand, in the shift register unit circuit A1, the second clocked inverter 102 is in the high impedance state, and, in the shift register unit circuit A2, the first clocked inverter 101 is in the high impedance state in which its input is in the H level.
From this state, if the first clock signal CK1 becomes the L level and the second clock signal CK2 becomes the H level, in the shift register unit circuit A1, the first clocked inverter 101 changes from the operation state as the inverter having the input of the H level and the output of the L level to the high impedance state. Simultaneously, the second clocked inverter 102 changes from the high impedance state to the operation state as the inverter having the input of the H level and the output of the L level. Therefore, in the shift register unit circuit A1, a latch circuit is constituted by the second clocked inverter 102 and the inverter 103, and the output of the output signal P1 still maintains the H level.
On the other hand, in the shift register unit circuit A2, the first clocked inverter 101 changes from the high impedance state, in which its input is in the H level, to the operation state as the inverter having the input of the H level and the output of the L level, and the output of the output signal P2 becomes the H level.
Subsequently, from this state, if the second clock signal CK2 becomes the L level and the first clock signal CK1 becomes the H level, in the shift register unit circuit A1, the first clocked inverter 101 changes from the high impedance state to the operation state as an inverter having the input of the L level and the output of the H level. Simultaneously, the second clocked inverter 102 changes from the operation state as the inverter having the input of the H level and the output of the L level to the high impedance state. Therefore, the output of the output signal P1 becomes the L level.
On the other hand, in the shift register unit circuit A2, a latch circuit is constituted, and then the output of the output signal P2 still maintains the H level. Further, in the shift register unit circuit A3, the output of the output signal P3 changes from the L level to the H level.
As such, the timing at which each of the output signals P1 to Pn in the respective shift register unit circuits A1 to An changes from the L level to the H level is determined by the timing at which the first clocked inverter 101 changes from the high impedance state, in which its input is in the H level, to the ON state.
Further, the timing at which each of the output signals P1 to Pn changes from the H level to the L level is determined by the timing at which the first clocked inverter 101 changes from the high impedance state, in which its input is in the L level, to the ON state.
Next, when the bidirectional shift register is constituted in the negative logic, the operations of the shift register unit circuits A1 to A4 will be described.
It is assumed that the transmission start pulse ST, which is in an active state at the time of the L level, is input, the first clock signal CK1 is in the H level, and the second clock signal CK2 is in the L level.
In this state, in the shift register unit circuit A1, the first clocked inverter 101 operates as an inverter having the input of the L level and the output of the H level (high level), and the output of the output signal P1 is in the L level.
On the other hand, in the shift register unit circuit A1, the second clocked inverter 102 is in the high impedance state, and, in the shift register unit circuit A2, the first clocked inverter 101 is also in the high impedance state, in which its input is in the L level.
From this state, if the first clock signal CK1 becomes the L level and the second clock signal CK2 becomes the H level, in the shift register unit circuit A1, the first clocked inverter 101 changes from the operation state as the inverter having the input of the L level and the output of the H level to the high impedance state. Simultaneously, the second clocked inverter 102 changes from the high impedance state to the operation state as the inverter having the input of the L level and the output of the H level. Therefore, in the shift register unit circuit A1, a latch circuit is constituted by the second clocked inverter 102 and the inverter 103, and the output of the output signal P1 still maintains the L level.
On the other hand, in the shift register unit circuit A2, the first clocked inverter 101 changes from the high impedance state, in which its input is in the L level, to the operation state as the inverter having the input of the L level and the output of the H level, and the output of the output signal P2 becomes the L level.
Subsequently, from this state, if the second clock signal CK2 becomes the L level and the first clock signal CK1 becomes the H level, in the shift register unit circuit A1, the first clocked inverter 101 changes from the high impedance state to the operation state as an inverter having the input of the H level and the output of the L level. Simultaneously, the second clocked inverter 102 changes from the operation state as the inverter having the input of the L level and the output of the H level to the high impedance state. Therefore, the output of the output signal P1 becomes the H level.
On the other hand, in the shift register unit circuit A2, a latch circuit is constituted, and the output of the output signal P2 still maintains the L level. Further, in the shift register unit circuit A3, the output of the output signal P3 changes from the H level to the L level.
As such, the timing at which each of the output signals P1 to Pn in the respective shift register unit circuits A1 to An changes from the H level to the L level is determined by the timing at which the first clocked inverter 101 changes the high impedance state, in which its input is in the L level, to the ON state.
Further, the timing at which each of the output signals P1 to Pn changes from the L level to the H level is determined by the timing at which the first clocked inverter 101 changes the high impedance state, in which its input is in the H level, to the ON state.
1-1: Configuration of Inverter
The inverter constituting each of the above-described shift register unit circuits A1 to An has the following configuration.
FIG. 15 is a circuit diagram of the inverter at a transistor level.
The inverter is a CMOS type in which a p-channel MOS transistor 111 (hereinafter, referred to as pMOS) and an n-channel MOS transistor 112 (hereinafter, referred to as nMOS) are combined. Specifically, gates of the pMOS 111 and the nMOS 112 are connected to an input terminal, and drains of the pMOS 111 and the nMOS 112 are connected to an output terminal.
In this inverter, when an input is in the H level, the pMOS 111 is turned off and the nMOS 112 is turned on. If doing so, a voltage on the nMOS 112 appears on the output terminal, and thus an output becomes the L level. On the other hand, when the input is in the L level, the nMOS 112 is turned off and the pMOS 111 is turned on. If doing so, a voltage on the PMOS 111 appears on the output terminal, and thus the output becomes the H level.
1-2: Configuration of Clocked Inverter Operating by First Clock Signal
The clocked inverter which constitutes each of the above-described transistor unit circuits A1 to An and which operates when the first clock signal CK1 is in the H level has the following configuration.
FIG. 16 is a circuit diagram of the clocked inverter, which operates by the first clock signal CK1, at a transistor level.
The clocked inverter is constituted by connecting two pMOS and two nMOS in series. Specifically, a second pMOS 113, a first pMOS 111, a first nMOS 112, and a second nMOS 114 are connected in that order. The first pMOS 111 and the first nMOS 112 have the same configuration as that of the above-described inverter. Further, since the clocked inverter operates when the first clock signal CK1 is in the H level, the first inverted clock signal CK1B is supplied to the second pMOS 113, and the first clock signal CK1 is supplied to the second nMOS 114.
The operation of the clocked inverter, which operates by the first clock signal CK1, is divided into four modes described below.
(1-1) When the input level is H, the second nMOS 114 becomes the ON state by the first clock signal CK1, and the clocked inverter changes from the high impedance state to the ON state.
(1-2) When the input level is H, the second nMOS 114 becomes the OFF state by the first clock signal CK1, and the clocked inverter changes from the ON state to the high impedance state.
(1-3) When the input level is L, the second pMOS 113 becomes the ON state by the first inverted clock signal CK1B, and the clocked inverter changes from the high impedance state to the ON state.
(1-4) When the input level is L, the second pMOS 113 becomes the OFF state by the first inverted clock signal CK1B, and the clocked inverter changes from the ON state to the high impedance state.
1-3: Configuration of Clocked Inverter Operating by Second Clock Signal
FIG. 17 is a circuit diagram of the clocked inverter, which operates by the second clock signal CK2, at a transistor level.
The clocked inverter substantially has the same configuration as that of the clocked inverter, which operates by the first clock signal CK1, but operates if the second clock signal CK2 becomes the H level. Accordingly, the second inverted clock signal CK2B is supplied to the second pMOS 113, and the second clock signal CK2 is supplied to the second nMOS 114.
The operation of the clocked inverter, which operates by the second clock signal CK2 is divided into four modes described below.
(2-1) When the input level is H, the second nMOS 114 becomes the ON state by the second clock signal CK2, and the clocked inverter changes from the high impedance state to the ON state.
(2-2) When the input level is H, the second nMOS 114 becomes the OFF state by the second clock signal CK2, and the clocked inverter changes from the ON state to the high impedance state.
(2-3) When the input level is L, the second PMOS 113 becomes the ON state by the second inverted clock signal CK2B, and the clocked inverter changes from the high impedance state to the ON state.
(2-4) When the input level is L, the second pMOS 113 becomes the OFF state by the second inverted clock signal CK2B, and the clocked inverter changes from the ON state to the high impedance state.
1-4: Inverted Clock Signal Generating Circuit
Specifically, the inverted clock signals, which are supplied to the above-described clocked inverters, are generated by an inverted clock signal generating circuit 120 to be described below.
FIG. 18 is a circuit diagram of the inverted clock signal generating circuit 120.
The inverted clock signal generating circuit has an inverter 121, and capacitors 122 and 123 that are parasitic on wiring lines of input and output sides. The inverter 121 has the same configuration as that of the inverter shown in FIG. 15.
If the clock signals CK1 and CK2 are supplied to the inverter 121, the clock signals CK1 and CK2 are inverted by the inverter 121, such that the inverted clock signals CK1B and CK2B are obtained.
By the way, in the pMOS and the nMOS, there is the difference in hole mobility and electron mobility, and thus the pMOS and the nMOS have different voltage levels of the ON/OFF operation, that is, the threshold values.
Accordingly, the inverted clock signals CK1B and CK2B are generated by use of the inverted clock signal generating circuit shown in FIG. 18. The inverted clock signals CK1B and CK2B have delay time Td with respect to the clock signals CK1 and CK2, respectively, as shown in FIGS. 19 and 20.
That is, even when the clock signals CK1 and CK2 start to change from the H level to the L level, there is no case in which the pMOS and the nMOS constituting the inverter are immediately turned on and off, respectively. Specifically, at a level decreased by a constant voltage, the pMOS is turned on with a timing earlier than a timing at which the nMOS is turned off. If doing so, the voltage on the pMOS appears on the output terminal, and then the inverted clock signals CK1B and CK2B start to change from the L level to the H level.
Further, even when the clock signals CK1 and CK2 start to change from the L level to the H level, there is no case in which the pMOS and the nMOS constituting the inverter are immediately turned off and on, respectively. Then, at a level increased by a constant voltage, the voltage on the pMOS appears on the output terminal until the pMOS is turned off, and the inverted clock signals CK1B and CK2B maintain the H level.
Accordingly, the delay time Td is present between a rising edge of the clock signal CK1 or CK2 and a rising edge of the inverted clock signal CK1B or CK2B. Further, the delay time Td is present between a falling edge of the clock signal CK1 or CK2 and a falling edge of the inverted clock signal CK1B or CK2B. Here, the H-level periods of the clock signals CK1 and CK2 are set so as not to overlap each other.
1-5: Influence of Clock Signal and Inverted Clock Signal on Output Signal
The clock signals CK1 and CK2, and the inverted clock signals CK1B and CK2B having delay time Td with respect to the clock signals CK1 and CK2 are supplied to the bidirectional shift register 100.
FIG. 19 is a timing chart when the bidirectional shift register is constituted in a positive logic.
In an odd-numbered shift register unit circuit A of the shift register unit circuits A1 to An, when the first clock signal CK1 becomes the H level, the input of the first clocked inverter 101 changes from the high impedance state of the H level to the ON state. Accordingly, at the time T1A or T3A, an odd-numbered output signal P changes from the L level to the H level when the second nMOS 114 becomes the ON state by the first clock signal CK1 (1-1).
On the other hand, in the odd-numbered shift register unit circuit A, when the first clock signal CK1 becomes the H level, the input of the first clocked inverter 101 changes from the high impedance state of the L level to the ON state. Accordingly, at the time T4A or T7A, the odd-numbered output signal P changes from the H level to the L level when the second pMOS 113 becomes the ON state by the first inverted clock signal CKLB (1-3).
Further, in an even-numbered shift register unit circuit A of the shift register unit circuits A1 to An, when the second clock signal CK2 becomes the H level, the input of the first clocked inverter 101 changes from the high impedance state of the H level to the ON state. Accordingly, at the time T2A or T5A, an even-numbered output signal P changes from the L level to the H level when the second nMOS 114 becomes the ON state by the second clock signal CK2 (2-1).
On the other hand, in the even-numbered shift register unit circuit A, when the second clock signal CK2 becomes the H level, the input of the first clocked inverter 101 changes from the high impedance state of the L level to the ON state. Accordingly, at the time T6A or T8A, the even-numbered output signal P changes from the H level to the L level when the second pMOS 113 becomes the ON state by the second inverted clock signal CK2B (2-3).
Therefore, when the bidirectional shift register is constituted in the positive logic, the pulse width of each of the output signals P becomes Tp+Td.
FIG. 20 is a timing chart when the bidirectional shift register is constituted in a negative logic.
In the odd-numbered shift register unit circuit A of the shift register unit circuits A1 to An, when the first clock signal CK1 becomes the H level, the input of the first clocked inverter 101 changes from the high impedance state of the L level to the ON state. Accordingly, at the time T1B or T4B, the odd-numbered output signal P changes from the H level to the L level when the second pMOS 113 becomes the ON state by the first inverted clock signal CK1B (1-3).
On the other hand, in the odd-numbered shift register unit circuit A, when the first clock signal CK1 becomes the H level, the input of the first clocked inverter 101 changes from the high impedance state of the H level to the ON state. Accordingly, at the time T3B or T7B, the odd-numbered output signal P changes from the L level to the H level when the second nMOS 114 becomes the ON state by the first clock signal CK1 (1-1).
Further, in the even-numbered shift register unit circuit A of the shift register unit circuits A1 to An, when the second clock signal CK2 becomes the H level, the input of the first clocked inverter 101 changes from the high impedance state of the L level to the ON state. Accordingly, at the time T2B or T6B, the even-numbered output signal P changes from the H level to the L level when the second pMOS 113 becomes the ON state by the second inverted clock signal CK2B (2-3).
On the other hand, in the even-numbered shift register unit circuit A, when the second clock signal becomes the H level, the input of the first clocked inverter 101 changes from the high impedance state of the H level to the ON state. Accordingly, at the time T5B or T8B, the even-numbered output signal P changes from the L level to the H level when the second nMOS 114 becomes the ON state by the second clock signal CK2 (2-1).
Therefore, when the bidirectional shift register is constituted in the negative logic, the pulse width of each of the output signals P becomes Tp−Td.
Then, the pulse widths of the output signals P in the positive-logic and negative-logic bidirectional shift registers differ from each other by 2Td. For this reason, if the above-described bidirectional shift register is used as, for example, a data line driving circuit, the change in pulse width of the output signals needs to be considered at the time of the change of design, and design working takes much time.